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Timing
Statistical timing analysis is an area of growing importance in nanometer te- nologies‚ as the uncertainties associated with process and environmental var- tions increase‚ and this chapter has captured some of the major efforts in this area. This remains a very active field of research‚ and there is likely to be a great deal of new research to be found in conferences and journals after this book is published. In addition to the statistical analysis of combinational circuits‚ a good deal of work has been carried out in analyzing the effect of variations on clock skew. Although we will not treat this subject in this book‚ the reader is referred to [LNPS00‚ HN01‚ JH01‚ ABZ03a] f...
Routing Congestion in VLSI Circuits
This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.
Timing Analysis and Optimization of Sequential Circuits
Recent years have seen rapid strides in the level of sophistication of VLSI circuits. On the performance front, there is a vital need for techniques to design fast, low-power chips with minimum area for increasingly complex systems, while on the economic side there is the vastly increased pressure of time-to-market. These pressures have made the use of CAD tools mandatory in designing complex systems. Timing Analysis and Optimization of Sequential Circuits describes CAD algorithms for analyzing and optimizing the timing behavior of sequential circuits with special reference to performance parameters such as power and area. A unified approach to performance analysis and optimization of sequen...
Circadian Rhythms for Future Resilient Electronic Systems
This book describes methods to address wearout/aging degradations in electronic chips and systems, caused by several physical mechanisms at the device level. The authors introduce a novel technique called accelerated active self-healing, which fixes wearout issues by enabling accelerated recovery. Coverage includes recovery theory, experimental results, implementations and applications, across multiple nodes ranging from planar, FD-SOI to FinFET, based on both foundry provided models and predictive models. Presents novel techniques, tested with experiments on real hardware; Discusses circuit and system level wearout recovery implementations, many of these designs are portable and friendly to the standard design flow; Provides circuit-architecture-system infrastructures that enable the accelerated self-healing for future resilient systems; Discusses wearout issues at both transistor and interconnect level, providing solutions that apply to both; Includes coverage of resilient aspects of emerging applications such as IoT.
Computer Aided Design and Design Automation
This volume of The Circuits and Filters Handbook, Third Edition focuses on computer aided design and design automation. In the first part of the book, international contributors address topics such as the modeling of circuit performances, symbolic analysis methods, numerical analysis methods, design by optimization, statistical design optimization, and physical design automation. In the second half of the text, they turn their attention to RF CAD, high performance simulation, formal verification, RTK behavioral synthesis, system-level design, an Internet-based micro-electronic design automation framework, performance modeling, and embedded computing systems design.
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
This book constitutes the thoroughly refereed post-conference proceedings of 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008, featuring Integrated Circuit and System Design, held in Lisbon, Portugal during September 10-12, 2008. The 31 revised full papers and 10 revised poster papers presented together with 3 invited talks and 4 papers from a special session on reconfigurable architectures were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-leakage and subthreshold circuits, low-power methods and models, arithmetic and memories, variability and statistical timing, synchronization and interconnect, power supplies and switching noise, low-power circuits; reconfigurable architectures, circuits and methods, power and delay modeling, as well as power optimizations addressing reconfigurable architectures.
Logic Synthesis and Verification
Research and development of logic synthesis and verification have matured considerably over the past two decades. Many commercial products are available, and they have been critical in harnessing advances in fabrication technology to produce today's plethora of electronic components. While this maturity is assuring, the advances in fabrication continue to seemingly present unwieldy challenges. Logic Synthesis and Verification provides a state-of-the-art view of logic synthesis and verification. It consists of fifteen chapters, each focusing on a distinct aspect. Each chapter presents key developments, outlines future challenges, and lists essential references. Two unique features of this boo...
EDA for IC Implementation, Circuit Design, and Process Technology
Presenting a comprehensive overview of the design automation algorithms, tools, and methodologies used to design integrated circuits, the Electronic Design Automation for Integrated Circuits Handbook is available in two volumes. The second volume, EDA for IC Implementation, Circuit Design, and Process Technology, thoroughly examines real-time logic to GDSII (a file format used to transfer data of semiconductor physical layout), analog/mixed signal design, physical verification, and technology CAD (TCAD). Chapters contributed by leading experts authoritatively discuss design for manufacturability at the nanoscale, power supply network design and analysis, design modeling, and much more. Save on the complete set.
Energy Efficient and Reliable Embedded Nanoscale SRAM Design
This reference text covers a wide spectrum for designing robust embedded memory and peripheral circuitry. It will serve as a useful text for senior undergraduate and graduate students and professionals in areas including electronics and communications engineering, electrical engineering, mechanical engineering, and aerospace engineering. Discusses low-power design methodologies for static random-access memory (SRAM) Covers radiation-hardened SRAM design for aerospace applications Focuses on various reliability issues that are faced by submicron technologies Exhibits more stable memory topologies Nanoscale technologies unveiled significant challenges to the design of energy- efficient and rel...
Post-Silicon and Runtime Verification for Modern Processors
The purpose of this book is to survey the state of the art and evolving directions in post-silicon and runtime verification. The authors start by giving an overview of the state of the art in verification, particularly current post-silicon methodologies in use in the industry, both for the domain of processor pipeline design and for memory subsystems. They then dive into the presentation of several new post-silicon verification solutions aimed at boosting the verification coverage of modern processors, dedicating several chapters to this topic. The presentation of runtime verification solutions follows a similar approach. This is an area of processor design that is still in its early stages of exploration and that holds the promise of accomplishing the ultimate goal of achieving complete correctness guarantees for microprocessor-based computation. The authors conclude the book with a look towards the future of late-stage verification and its growing role in the processor life-cycle.
